[Bolo]

Small R&D info ))

Movie presents proof of concept of new software for Voltage Offsets in QLC (SDR/DDR2) memory. Readed on standard FE reader with internal voltage (3.3V) - ID 0x2c d4 0c 32 / 0x89 d4 0c 32

YouTube link - https://www.youtube.com/watch?v=e-dSrPAWkdc

Explanation:
In QLC chips there are four pages - Low Page, Upper Page, eXtra Page, Top Page. While "Low Page" can be usually corrected by any reader then 3 other pages are uncorrectable due RR registry cannot be properly set. This is more often by Green/Red stripes on ECC Map (0:20). In our laboratory we created special software that are able to adjust proper Voltage Offsets for "Upper Page", "eXtra Page" and "Top Page" one-by-one. After this correction (ECC) for such memory takes much less time.

On Movie you see already fixed image (full green) by us already. Then we jump into normal read which you usually can get with build on functions (first page green, all 3 rest red - stripes) and then magic starts.... voltage offsets regulation for each page ))))

Soon PoC for DDR3 ))

In case you got QLC chips which above issues feel free to contact us.

[jeremyb]

I really like the app, it's very slick.
Good explanation..

I don't see what actual R&D you've done though. Micron v3 (TLC) registers support this, you just added the remaining QLC (for SDR) registers... Nothing special. Kind of an insult saying send your work exclusively to me for RR that anyone can do. If you'd like Sergey can implement the registers in the next version of FE. Micron v4 supports TLC, QLC, and DQS QLC.. so big deal..

If you want a challenge I have a few 1.2v DDR3 QLC NAND chips w/ DQS..
I can read 50% of the data but there are still random bit errors, no stripes.. If you can read them I'll give you credit

[Bolo]

Micron v3 not work here - if need movie we can record it. Main diffrence in our method for those chips is that we don’t set any additonal RR registers (as you see we registers works on Micron v2). What we do is we are changing voltage offsets here and for SDR it can work on standard FE reader on 3.3V. No Power mod needed even.

For DDR3 /DQS we Already write in comments that soon we will publish PoC

[jeremyb]

Micron v3 is for TLC not QLC of course it won't work.. Adding QLC regs is no problem though.. just saying.. it's a little presumptuous to say, only we can implement this RR.

Power mod is only not required on a select few NAND chips...

Slick app though.

[Bolo]

We never say that only we can implement this… this movie is proof of concept for voltage offsets registers instead of ReadRetry registers which are totally two diffrent aspect of correction of NAND. This is why it can work on normal reader.

[jeremyb]